Rygar — The CPU

arcade Nov 10, 2020

The most critical part of the entire arcade hardware design is undoubtedly the CPU. Without it, nothing else would function — there would be no graphics, no sound, and no game logic. Its job is fairly simple: fetch instructions from memory, execute them, and tell all the other subsystems what to do.

The Zilog Z80 is an 8-bit microprocessor that was developed by Federico Faggin (an ex-Intel engineer) in 1976. It has an 8-bit data bus, which means that it can only read or write a single byte to the data bus at a time. It also has a 16-bit address bus, so it can address up to 64KB of memory. These features, and the relatively low cost of the Z80, made it a popular choice for early arcade game engineers.

Consequently, many arcade games, video game consoles, and home computers designed in the 80s and 90s contain at least one Z80 CPU — employed either as the main processor and/or as a coprocessor — and are typically used to handle duties like graphics, sound, game logic, etc.

Rygar is no exception, it contains two Z80 CPUs: one for running the main program (i.e. the game), and one dedicated to handling sound.

Let's have a look at the page in the Rygar schematic that describes the main CPU (the complete schematic is ten pages), it has been marked it up with the most important features.

Here we can see the main CPU hooked up to the 4MHz clock, the data and address buses, work RAM, main program ROMs, and some address decoding logic.

What are all these things for?

Clock

The 4MHz clock signal is generated by a crystal oscillator. There are a few inverters which buffer the signal, but interestingly there are also a couple of jumpers that allow the clock to be switched to 6MHz.

The fact that the clock frequency can be switched is a clue that this board may support other games. If we cheat for a moment and look at the MAME source code, we can see that Silkworm indeed runs the main CPU at 6MHz. Looks like this theory checks out.

Data and Address Buses

The data and address buses are the set of signals that the CPU uses to move data between the other subsystems (e.g. memory, graphics, sound, IO, etc.). You'll see the data bus (D0-7) and the address bus (A0-15) signals appear on most pages in the schematic.

In the schematic, we can see there is a custom chip labelled "T-1 HYBRID IC 28-PIN". Because I don't actually have a Rygar PCB, I wasn't able to verify what this chip does exactly, but it is a custom device designed by Tecmo.

My guess is that it allows the data bus to be tri-state, so it can be used by the CPU as an input, output, or put into a high-impedance (Hi-Z) state.

Program ROM

There are many ROMs on the PCB that are used to store things like game data, graphics tiles, PCM samples, etc. The program ROM is where the actual instructions that are executed by the CPU are stored.

Interestingly, there are two physical ROM chips that make up the 48KB main program ROM: a 27256 (32KB) and a 27128 (16KB). This is likely either due to cost or supply issues back in 1986, as later Tecmo games like Silkworm just used a single 64KB chip for the program ROM.

I should also point out that the CPU doesn't have direct access to the other ROM chips on the PCB. They are only accessible by particular subsystems — for example, tiles ROMs are accessed by the graphics subsystem, the PCM sample ROM by the sound subsystem, etc.

Work RAM

There are also multiple RAM chips on the Rygar PCB. The work RAM is used by the CPU to store temporary things like the call stack, variables (e.g. player position, lives, etc.), data structures (e.g. level data), counters, etc.

We can see in the schematic that the work RAM is a HM6264 chip, which is an 8KB static RAM.

Address Decoding

Because the memory devices and other subsystems are all connected to the same data and address buses, there needs to be logic to coordinate bus access. You can't have everything talking on the bus at the same time!

Most of the devices you see in the main CPU schematic, which aren't the CPU or RAM/ROM, are used for address decoding.

The address decoding logic looks at the values on the address bus and decides which device or subsystem the CPU is trying to talk to.

When I was trying to reverse engineer Rygar, this is the part where I sat down with coloured pens and traced the signals out. Once you figure out the memory address ranges in which particular devices are active, you can create something called a memory map.

For example, it might looks something like this:

$0000-$bfff: PROGRAM ROM
$c000-$cfff: WORK RAM
$d000-$dfff: CHARACTER RAM
...

This means that for the addresses from $0000 to $bfff, the program ROM will be active. If the CPU reads data from the data bus while the address is in that range, it will be reading data from the program ROM.

The memory map is a topic worthy of it's own post, so I'm going to leave it here for now and we'll pick it up in the next one.

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Josh Bassett

Hello. I'm a software developer living in Byron Bay, Australia.